Tutorial

Mastering AXI4-Lite with YAML Configuration

By Axion Team • 8 min read

For larger projects, defining registers in a separate configuration file can help separate interface definition from implementation. Axion-HDL supports a clean, human-readable YAML format for this purpose.

1. Create the YAML Config

Create a file named i2c.yaml. Define your module name, base address, and list your registers. You can specify access types (RW, RO, WO), strobes, and descriptions.

module: i2c_master
base_addr: "0x2000"
config:
  cdc_en: true

registers:
  - name: control
    addr: "0x00"
    access: RW
    w_strobe: true
    description: "I2C Control Register"

  - name: status
    addr: "0x04"
    access: RO
    r_strobe: true
    description: "I2C Status Register"

  - name: data
    addr: "0x08"
    access: RW
    description: "I2C Data Register"

2. Generate Everything

Run the tool pointing to your YAML file.

$ axion-hdl -s tutorial_yaml/ -o output/ --all

Parsing YAML file: tutorial_yaml/i2c.yaml
Found 1 modules from YAML files.

Module: i2c_master
CDC: Enabled (Stages: 2)
Total Registers: 3

✓ i2c_master_axion_reg.vhd
✓ i2c_master_regs.h
✓ i2c_master_regs.yaml

→ All files generated successfully!

3. The Output

Axion-HDL generates a complete VHDL entity handling the AXI4-Lite protocol logic, address decoding, and CDC synchronization.

entity i2c_master_axion_reg is
    generic (
        BASE_ADDR : std_logic_vector(31 downto 0) := x"00002000"
    );
    port (
        -- AXI4-Lite Interface
        axi_aclk    : in  std_logic;
        axi_aresetn : in  std_logic;
        -- ... standard AXI ports ...
        
        -- Register Signals
        control : out std_logic_vector(31 downto 0);
        control_wr_strobe : out std_logic;
        status : in  std_logic_vector(31 downto 0);
        status_rd_strobe : out std_logic;
        data : out std_logic_vector(31 downto 0)
    );
end entity i2c_master_axion_reg;

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