Tutorial

How to Generate AXI4-Lite Registers with VHDL Annotations

By Axion Team • 10 min read

One of the most powerful features of Axion-HDL is the ability to define your register interface directly inside your VHDL source code. This eliminates context switching between format converters or external Excel sheets.

1. Define Your Registers

Start with a standard VHDL entity. Add the @axion_def comment at the top to define the base address and configuration options. Then, use @axion comments above your signals to define registers.

-- @axion_def BASE_ADDR=0x1000 CDC_EN
library ieee;
use ieee.std_logic_1164.all;

entity uart_controller is
    port (
        clk     : in std_logic;
        rst     : in std_logic;
        tx      : out std_logic;
        rx      : in std_logic
    );
end entity uart_controller;

architecture rtl of uart_controller is
    
    -- Control Register
    -- @axion RW W_STROBE DESC="UART Control Register"
    signal control : std_logic_vector(31 downto 0);
    
    -- Status Register
    -- @axion RO R_STROBE DESC="UART Status Register"
    signal status : std_logic_vector(31 downto 0);
    
    -- Data Registers
    -- @axion WO DESC="Transmit Data"
    signal tx_data : std_logic_vector(31 downto 0);
    -- @axion RO DESC="Receive Data"
    signal rx_data : std_logic_vector(31 downto 0);

begin

2. Generate the Interface

Run the axion-hdl tool in your terminal, pointing to your source directory.

$ axion-hdl -s src/ -o output/ --all

✓ uart_controller_axion_reg.vhd
✓ uart_controller_regs.h
✓ uart_controller_regs.yaml

→ All files generated successfully!

3. Integrate into Your Design

Finally, instantiate the generated component uart_controller_axion_reg in your architecture and connect the register signals.

begin

    component uart_controller_axion_reg is
        -- ... Generated declarations ...
    end component;

    inst_regs : uart_controller_axion_reg
    port map (
        axi_aclk    => clk,
        axi_aresetn => rst_n,
        -- Connect AXI Master ...
        
        -- Connect Registers
        control => control,
        status  => status,
        tx_data => tx_data,
        rx_data => rx_data
    );

end architecture;

Try it Now