Automate AXI register generation for FPGA and ASIC. Create AXI4-Lite register interfaces from VHDL annotations, YAML, XML, JSON, or TOML. Built-in CDC synchronizers, subregisters, and complete documentation.
pip install axion-hdl
$ axion-hdl -s pwm_controller.sv -o output/ --vhdl --sv --c-header
# Generated files:
✓ pwm_controller_axion_reg.vhd AXI4-Lite slave (VHDL)
✓ pwm_controller_axion_reg.sv AXI4-Lite slave (SV)
✓ pwm_controller_regs.h C header
→ All files generated successfully!From simple LED controllers to complex SoC peripherals — Axion-HDL handles it all.
Define registers in VHDL or SystemVerilog annotations, YAML, XML, JSON, or TOML. Use whatever fits your workflow.
Built-in 2/3/4-stage clock domain crossing. Safe register access across clock domains.
Pack multiple bit fields into a single address. Perfect for status/control registers.
Automatically split 64-bit+ signals across multiple addresses. No manual splitting needed.
Generate pulse signals for register access. Ideal for FIFOs and interrupt handlers.
Auto-generate Markdown docs, C headers, and IP-XACT XML for every register map.
Parse annotations from .sv source files and generate register interfaces in SystemVerilog or VHDL — your pick.
Pick the interface that suits your workflow best.
Perfect for scripts and CI/CD pipelines. Fast, scriptable, and easy to integrate.
axion-hdl -s src/ -o output/ --all
Full programmatic control for custom workflows and tool integration.
from axion_hdl import AxionHDL
Interactive visual editor for register maps. Great for exploration and prototyping.
pip install axion-hdl[gui]
Edit the register definition below and click Generate to see real output.
Click "Generate" to run axion-hdl...Generated VHDL will appear here...